This invention relates to bias error adjustment circuits of the type utilized in successive ranged digital/analog converter (SRADC) systems and in particular to a digital hysteresis circuit for eliminating noise induced hunting in these and other systems.
In a successively ranged analog/digital converter several bits are converted at a time in order to increase the speed over that of a successive approximation analog/digital converter which converts one bit at a time. In the SRADC type of device analog input signals are processed through an analog chain and fed to an n bit parallel analog/digital converter. The analog chain is the portion of the SRADC that determines the maximum operating speed. In order to reduce the propagation time through the analog chain the highest speed amplifiers available are utilized and hot carrier diode switches are used for gain switching. Also the amplifiers are operated over as low an output voltage swing as is feasible. These measures tend to increase bias errors, however. Hot carrier diode switches inherently produce bias errors, high speed amplifiers do not necessarily have good d.c. characteristics and the ratio of output offset to true signal is increased.
The input to the n bit parallel analog/digital converter goes through its range of possible voltage levels in every sub-range as the analog input goes through its full dynamic range. Bias errors in the analog chain can produce saturation of the analog/digital converter in some sub-ranges for a given analog input. This produces discontinuities in the final/digital converter output. Automatic bias correction circuits that obviate the adverse effects of the foregoing enumerated sources of bias error are described in our co-pending patent application entitled AUTOMATIC BIAS ADJUSTMENT CIRCUIT FOR A SUCCESSIVE RANGED ANALOG/DIGITAL CONVERTER, Ser. No. 898,047, filed on even date herewith. Although these circuits represent a substantial improvement over prior art approaches to the problem, the bias correction voltages generated by them hunt about normal levels due to noise and gain errors. That is, the fact that the inputs to the system parallel analog/digital converter at the end of each sub-range are not compact due to noise and gain errors causes the up/down counters to be enabled in a somewhat random fashion. Although the action will not cause the sub-ranges to be off center since the average values of the digital/analog outputs are correct, the hunting action that occurs is objectionable and must be eliminated. The digital hysteresis circuit of the invention provides the means for achieving that end.